Pamukkale Univ Muh Bilim Derg. Ahead of Print: PAJES-95694 | DOI: 10.5505/pajes.2025.95694

FPGA Prototyping: On-chip Debug Module for RISC-V Based SoC and Testing Processes Using Raspberry Pi with OpenOCD over JTAG

Sezen Bal¹, Hayriye Korkmaz², Doðukan Biçer³, Celal Alperen Bayar², Eren Kale², Eray Kayailli², Armaðan Bi^2
1Marmara University, Vocational School Of Technical Sciences, Department Of Computer Technologies, Istanbul
²Marmara University, Faculty Of Technology, Department Of Electrical And Electronics Engineering, Istanbul
³Marmara University, Institute Of Science And Technology, Department Of Electrical And Electronics Engineering, Istanbul

This paper presents the FPGA prototyping process of a RISC-V based System-on-Chip (SoC) design and the on-chip debug module integrated in this process. FPGA prototyping is the process of implementing and testing digital designs on an FPGA for hardware-level evaluation. In the study, debugging operations performed via JTAG using Raspberry Pi and OpenOCD are highlighted as a critical step to effectively test the various functions and performance of the SoC. This approach contributes to reduce costs in the development process and shorten time-to-market, while reducing the risks involved in the transition to the final silicon version of the design. The SoC design was executed on FPGA and subjected to various tests within the scope of functional verification and successful results were obtained. Functional verification is a critical testing phase to check whether a digital design exhibits the expected behavior. Within the scope of the floating point unit test, sine values were calculated by applying the sine function and the correct operation of the unit was verified. In the I2C peripheral test, a sensor was connected and it was determined that the data obtained from the sensor was received and processed correctly. The bit manipulation test showed that the RISC-V bit manipulation instructions worked correctly. In the FreeRTOS implementation, task scheduling, interrupts, and resource management were successfully implemented, and the system was verified to be error-free during multitasking. The correct operation of atomic operations and CSR (Control and Status Registers) was evaluated and verified to work as expected. In addition, the performance of the processor was evaluated using CoreMark and Dhrystone benchmarks. In the CoreMark test, the processor achieved a score of 41.97 iterations/second (600 iterations) and the CoreMark/MHz value was calculated as 2.51. In the Dhrystone benchmark, the processor performed 70.582 Dhrystones/second. The implementation of each component and the corresponding testbenches were wri tten in Verilog HDL and the design was implemented on a Terasic De10-Lite FPGA.

Keywords: RISC-V Processor, FPGA, Debug, System on Chip

---

FPGA Prototipleme: RISC-V Tabanlý SoC Ýçin Çip Üstü Hata Ayýklama Modülü ve Raspberry Pi ile OpenOCD JTAG Üzerinden Test Süreçleri

Sezen Bal¹, Hayriye Korkmaz², Doðukan Biçer³, Celal Alperen Bayar², Eren Kale², Eray Kayailli², Armaðan Bi^2
1Marmara Üniversitesi, Teknik Bilimler Meslek Yüksekokulu, Bilgisayar Teknolojileri Bölümü, Ýstanbul
²Marmara Üniversitesi, Teknoloji Fakültesi, Elektrik-Elektronik Mühendisliði Bölümü, Ýstanbul
³Marmara Üniversitesi, Fen Bilimleri Enstitüsü, Elektrik-Elektronik Mühendisliði Bölümü, Ýstanbul

Bu çalýþma, RISC-V tabanlý bir System-on-Chip (SoC) tasarýmýnýn FPGA üzerinde prototipleme sürecini ve bu süreçte entegre edilen çip üstü hata ayýklama modülünü ele almaktadýr. FPGA prototipleme, sayýsal tasarýmlarýn donaným seviyesinde deðerlendirilmesi amacýyla FPGA üzerinde uygulanmasý ve test edilmesi sürecidir. Çalýþmada, Raspberry Pi ve OpenOCD kullanýlarak JTAG aracýlýðýyla gerçekleþtirilen hata ayýklama iþlemleri, SoC'nin çeþitli fonksiyonlarýný ve performansýný etkin bir þekilde test etmek için kritik bir adým olarak vurgulanmaktadýr. Bu yaklaþým, geliþtirme sürecinde maliyetleri düþürmeye ve pazara sunma süresini kýsaltmaya katkýda bulunurken, tasarýmýn son silikon versiyonuna geçiþte karþýlaþýlacak riskleri azaltmaktadýr. SoC tasarýmý, FPGA üzerinde çalýþtýrýlarak fonksiyonel doðrulama kapsamýnda çeþitli testlere tabi tutulmuþ ve baþarýlý sonuçlar elde edilmiþtir. Fonksiyonel doðrulama, bir sayýsal tasarýmýn beklenen davranýþlarý sergileyip sergilemediðini kontrol etmek için uygulanan kritik bir test aþamasýdýr. Kayan nokta birimi testi kapsamýnda sinüs fonksiyonu uygulanarak sinüs deðerleri hesaplanmýþ ve birimin doðru çalýþtýðý doðrulanmýþtýr. I2C çevre birimi testinde, bir sensör baðlanarak sensörden elde edilen verilerin doðru þekilde alýndýðý ve iþlendiði tespit edilmiþtir. Bit manipulation testi, RISC-V bit manipülasyon komutlarýnýn doðru çalýþtýðýný göstermiþtir. FreeRTOS uygulamasýnda, görev zamanlamasý, kesmeler ve kaynak yönetimi baþarýyla gerçekleþtirilmiþ ve sistemin çoklu görev yürütme sýrasýnda hatasýz çalýþtýðý doðrulanmýþtýr. Atomik iþlemler ile CSR (Control and Status Registers) birimlerinin doðru iþleyiþi deðerlendirilmiþ ve beklendiði gibi çalýþtýðý doðrulanmýþtýr. Bunun yaný sýra, iþlemcinin performansý CoreMark ve Dhrystone kýyaslamalarý kullanýlarak deðerlendirilmiþtir. CoreMark testinde iþlemci, 41,97 iterasyon/saniye (600 iterasyon) skoruna ulaþmýþ ve CoreMark/MHz deðeri 2,51 olarak hesaplanmýþtýr. Dhrystone kýyaslamasýnda ise iþlemci, 70,582 Dhrystone/saniye performans sergilemiþtir. Her bir bileþenin implementasyonu ve ilgili test tezgahlarý Verilog HDL ile yazýlmýþ olup, tasarým Terasic De10-Lite FPGA üzerinde uygulanmýþtýr.

Anahtar Kelimeler: RISC-V Ýþlemci, FPGA, Hata Ayýklama, Çip üstü Sistem

---

CITE